This invention relates to a static random access memory (RAM) circuit, especially a static RAM circuit in which the data stored in a memory cell is read out by detecting the transition of an address signal level.
FIG. 3 shows a block diagram of a conventional static RAM circuit and FIG. 4 shows the timing chart thereof.
In FIGS. 3 and 4, in order to simplify the structure, only two address signals and only one memory cell are shown. Address signals AD.sub.0 and AD.sub.1 from the input terminals 1 and 2 are supplied to an address decoder 3 and a detecting pulse generator 4. The address decoder 3 is comprised of two inverters I.sub.1 and I.sub.2 and four AND gates A.sub.1 -A.sub.4, and word line selection signals AD.sub.0 .multidot.AD.sub.1, AD.sub.0 .multidot.AD.sub.1, AD.sub.0 .multidot.AD.sub.1 and AD.sub.0 .multidot.AD.sub.1 from the AND gates A.sub.1, A.sub.2, A.sub.3 and A.sub.4 are supplied to one input terminal of AND gates A.sub.5, A.sub.6, A.sub.7 and A.sub.8 respectively. These word line selection signals select any one of a plurality of word lines sequentially. The detecting pulse generator 4 is comprised of two detecting circuits D.sub.0 and D.sub.1 and an OR gate O.sub.1. The detecting circuit D.sub.0 detects a transition of the level of the address signal AD.sub.0. That is, when the address signal AD.sub.0 changes from an "H" level to an "L" level or an "L" level to an "H" level, the detecting circuit D.sub.1 detects such a transition and generates an address transition pulse (ATP.sub.0) as shown in FIG. 4. The detecting circuit D.sub.1 detects a transition of the level of the address signal AD.sub.1 in the same fashion as that of the detecting circuit D.sub.0 and generates an address transition pulse (ATP.sub.1). As a result, an address transition pulse (ATP) is delivered from the OR gate 0.sub.1 as shown in FIG. 4. The pulse width of the address transition pulse (ATP) is equal to the sum of the pulse width of the address transition pulses ATP.sub.0 and ATP.sub.1. A word line enable pulse generator 5 detects a trailing edge of the address transit pulse (ATP) and generates a word line enable pulse (WLE) as shown in FIG. 4. The word line enable pulse (WLE) is supplied to another input terminal of the AND gates A.sub.5 -A.sub.8. Consequently, any one of a plurality of word lines ( word line 6 in this case) selected by the AND gates A.sub.5 -A.sub.8 is enabled as shown in FIG. 4 "WL". On the other hand, the word line enable pulse (WLE) is supplied to the data transfer circuit 7 and the sense amplifier 8. Therefore, these circuits 7 and 8 are enabled at the same time when the selected word line 6 is enabled. When the selected word line 6 is enabled, the data stored in the memory cell 9 is readout to a bit line 10a so that the difference of the signal level between a pair of bit lines 10a and 10b as shown in FIG. 4 "BL" may be detected. The level difference between the bit lines 10a and 10b is transferred to a sense amplifier 8 as readout data through a data transfer circuit 7. The data is amplified by the sense amplifier 8, and the sense amplifier outputs (SAO, SAO) shown in FIG. 4 as "SAO" are supplied to an output buffer 11 and latched by the output buffer 11. After that, the output data (DATA) is supplied to the output terminal 12. When the word line enable pulse (WLE) terminates, the selected word line 6, the data transfer circuit 7 and the sense amplifier 8 are disabled, and the sense amplifier outputs (SAO, SAO) disappear. However, since the sense amplifier outputs (SAO, SAO) are latched by the output buffer 11, the output data (DATA) supplied to the output terminal 12 does not disappear after the extinction of the sense amplifier outputs (SAO, SAO) as shown in FIG. 4. When the word line enable pulse (WLE) terminates, all word lines, the data transfer circuit 7 and the sense amplifier 8 are disabled, and therefore, there is no waste of unnecessary current in the memory cells, the data transfer circuit 7 and the sense amplifier 8. Thus, the total current consumption is reduced.
Meanwhile, in FIGS. 3 and 4, only two address signals AD.sub.0 and AD.sub.1 and only one memory cell 9 are shown. However, in practical static RAM circuits, a plurality of memory cells are arranged in matrix, and a plurality of address signals are supplied to the input terminals so as to sequentially select necessary memory cells from among a plurality of memory cells.
As mentioned above, in a conventional static RAM circuit, the word line enable pulse (WLE) is generated by detecting the edge of the address transition pulse (ATP). The reason is as follows. In a practical static RAM circuit, the address signals (AD.sub.0, AD.sub.1, etc.) are often delayed from the predetermined timing because of parasitic capacitance, etc. This phenomenon is called "skew". When "skew" is caused, the pulse timing of the address transition pulses (ATP.sub.0, ATP.sub.1) are delayed, and the pulse timing of the address transition pulse (ATP) is also delayed according to the delay of the transition timing of the address signals (AD.sub.0, AD.sub.1, etc.). In order to avoid such "skew" phenomenon, in a conventional static RAM circuit, after receiving the transitions of all necessary address signals, in other words, after detecting the edge of the address transit pulse (ATP), the word line enable pulse (WLE) is generated.
However, under such a construction, the word line enabling timing (i.e. the term "t.sub.2 " in FIG. 4) is not determined by the operation speed of the address decoder 3 but determined by that of the detecting pulse generator 4 and the word line enable pulse generator 5. In order to shorten the term "t.sub.2 ", even if these generators 4 and 5 are designed to operate at high speed, so long as the word line enable pulse (WLE) is generated by detecting the trailing edge of the address transition pulse (ATP), it takes quite a bit time to generate the word line enable pulse (WLE). Therefore, in a conventional static RAM circuit, it is difficult to shorten the access time and to achieve a high speed operation.